`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   21:05:27 03/08/2010
// Design Name:   clock_generator
// Module Name:   F:/RAMCtrl/CellRAMController/clock_generator_tb.v
// Project Name:  CellRAMController
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: clock_generator
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module clock_generator_tb;

	// Inputs
	reg clock_in;
	reg reset;

	// Outputs
	wire clock_PS1;
	wire clock_PS2;
	wire clock_PS3;
	wire clock8;
	wire clk16;
	wire clock50;

	// Instantiate the Unit Under Test (UUT)
	clock_generator uut (
		.clock_in(clock_in), 
		.reset(reset), 
		.clock_PS1(clock_PS1), 
		.clock_PS2(clock_PS2), 
		.clock_PS3(clock_PS3), 
		.clock8(clock8), 
		.clk16(clk16), 
		.clock50(clock50)
	);
	
	always #10 clock_in = ~clock_in;

	initial begin
		// Initialize Inputs
		clock_in = 0;
		reset = 0;

		// Wait 100 ns for global reset to finish
		#100;
        #50	reset = 1;
		
		#50 reset = 0;
		
		#1000 $stop();
		
		// Add stimulus here

	end
      
endmodule

